This invention relates to electronic testing of one or more layers of an integrated semiconductor circuit.
Debugging of an array of flipchip devices, such as microprocessors and associated computer components implemented as integrated semiconductor circuits, is necessary to identify which devices are inoperative and the reason(s) for such device failures. One previous debug solution was to provide a large aperture in the flipchip package through which electronic probing could be performed. However, this now requires a full cut-out for the aperture, and any (power) solder bumps and circuit connections within the aperture become inoperative. Because of this lack of power-up, the chip cannot be tested or debugged at full speed.
What is needed is a device debugging approach that removes a minimal area aperture on a chip for signal testing or probing so that electrical power and continuity are not lost at solder bumps, circuit connections or other features within an aperture. Preferably, the location, shape and cross-sectional area of the aperture(s) should be flexible so that interference with a nearby circuit feature can be avoided or minimized, if desired.
These needs are met by the invention, which provides a plurality of small probe apertures in the semiconductor die, with locations strategically chosen to allow access to power core bumps and/or circuit connections that are part of the flipchip design. Any number of circuit layers, typically four or more, can be built up and tested for signal routing and power management. Circuit continuity and voltages at power points within a chip can be tested from a location outside the chip target region, using a socket or wire bond-flipchip connection to a package or to a substrate.
A protective coating or packaging material is preferably absent for the chip to be tested. However, a coating may be present, if the coating permits formation and resealing of small apertures therein for insertion of probe or test appliances. A controllably small aperture of arbitrary cross-sectional shape is etched or otherwise provided through one or more signal-processing layers of the chip to expose at least one circuit trace or electrical power solder bump at a target layer that is to be probed or otherwise tested. Optionally, two separated apertures can be provided so that a probe signal introduced at one point in a circuit is received and examined at another point in the circuit. The shape, size and location of the aperture can be chosen to minimize or avoid interference with provision of electrical power and/or electrical connections between circuit traces and components.